The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Aug. 30, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Ronald Allen Weimer, Boise, ID (US);

Toshihiko Miyashita, Higashihiroshima, JP;

Dan Mihai Mocuta, Boise, ID (US);

Christopher W. Petz, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/285 (2006.01); H01L 21/02 (2006.01); H10D 30/69 (2025.01); H10D 62/13 (2025.01); H10D 62/822 (2025.01); H10D 64/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/017 (2025.01); H01L 21/02532 (2013.01); H01L 21/28518 (2013.01); H10D 30/797 (2025.01); H10D 62/151 (2025.01); H10D 62/822 (2025.01); H10D 64/62 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract

A variety of applications can include apparatus having p-channel metal-oxide-semiconductor (PMOS) transistors and n-channel metal-oxide-semiconductor (NMOS) transistors with different metal silicide contacts. The active area of the NMOS transistor can include a first metal silicide having a first metal element, where the first metal silicide is a vertical lowest portion of a contact for the NMOS. The PMOS transistor can include a stressor source/drain region to a channel region of the PMOS transistor and a second metal silicide directly contacting the stressor source/drain region without containing the first metal element. The process flow to form the PMOS and NMOS transistors can enable making simultaneous contacts by a pre-silicide in the active area of the NMOS transistor, without affecting stressor source/drain regions in the PMOS transistor. The process flow and resulting structures for PMOS transistors and NMOS transistors can be used in various integrated circuits and devices.


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