The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Nov. 28, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Hong-Shyang Wu, Taipei, TW;

Kuo-Ming Wu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/60 (2025.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10D 64/00 (2025.01); H10D 62/17 (2025.01);
U.S. Cl.
CPC ...
H10D 64/118 (2025.01); H10D 30/0212 (2025.01); H10D 30/0221 (2025.01); H10D 30/0281 (2025.01); H10D 30/603 (2025.01); H10D 30/65 (2025.01); H10D 64/111 (2025.01); H10D 62/307 (2025.01);
Abstract

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.


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