The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Jun. 06, 2023
Applicant:

Walton Advanced Engineering, Inc., Kaohsiung, TW;

Inventors:

Hong-Chi Yu, Kaohsiung, TW;

Chun-Jung Lin, Kaohsiung, TW;

Ruei-Ting Gu, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/02 (2013.01); H01L 24/03 (2013.01); H01L 24/04 (2013.01); H01L 24/48 (2013.01); H01L 24/85 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/03602 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05026 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05562 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48105 (2013.01); H01L 2224/48464 (2013.01); H01L 2224/85 (2013.01);
Abstract

A chip package with higher bearing capacity in wire bonding is provided. The chip package includes at least one conductive circuit which is a structure with a thickness ranging from 4.5 μm to 20 μm. Thereby a structural strength of the conductive circuit is improved and able to stand a positive pressure generated in wire bonding or formation of a first bonding point. Thus at least one internal circuit of a chip will not be damaged by the positive pressure and allowed to pass through an area under the first bonding point or arrange under the first bonding point. A problem of increased cost at manufacturing end caused by the internal circuit redesign of the chip can be solved effectively. This is beneficial to cost reduction at manufacturing end.


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