The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Aug. 12, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Kuo-Chiang Ting, Hsinchu, TW;

Tu-Hao Yu, Hsinchu, TW;

Shun-Jang Laio, Pingjhen, TW;

Chien-Chung Wang, New Taipei, TW;

Chia-Ching Lin, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H10D 1/68 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 23/147 (2013.01); H01L 23/49816 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/0655 (2013.01); H10D 1/68 (2025.01); H01L 2224/16012 (2013.01); H01L 2224/16157 (2013.01); H01L 2224/32137 (2013.01); H01L 2224/73104 (2013.01);
Abstract

An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.


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