The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Dec. 07, 2023
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Ming Wang, Shanghai, CN;

Liang Li, Shanghai, CN;

Yichen Wang, Shanghai, CN;

Wei Li, Shanghai, CN;

Jiahui Yuan, Fremont, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3431 (2013.01); G06F 3/0613 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01);
Abstract

An apparatus includes a memory structure including non-volatile memory cells, and a control circuit coupled to the memory cell. The control circuit configured to first read a block of non-volatile memory cells using a first plurality of read levels, determine that the first read fails to successfully read the block of non-volatile memory cells, second read the block of memory cells using a second plurality of read levels different from the first plurality of read levels, determine that the second read successfully reads the block of non-volatile memory cells, estimate that the first read failed because of data retention or read disturb, and erase and re-write data to the block of non-volatile memory cells.


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