Apparatus, method and system to reduce memory window latency and read disturb in a memory device for memory operations

Abstract

A method, apparatus and system. The apparatus includes one or more processors to: determine that a memory operation including one of a write operation or a read operation is to be implemented on a memory cell of a memory array, the memory operation having a duration equal to a latency window and being based on a voltage change across the memory cell equal to a target memory window; and in response to a determination that the memory operation is to be implemented, cause, during the latency window, an application of a current pulse amplitude profile to the memory cell, wherein the current pulse amplitude profile decreases progressively, encompassing at least four different current pulse amplitudes, the at least four different current pulse amplitudes including a highest current pulse amplitude and a lowest current pulse amplitude.