The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Jun. 21, 2022
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Kuo-Hsing Lee, Hsinchu County, TW;

Chun-Hsien Lin, Tainan, TW;

Yung-Chen Chiu, Taichung, TW;

Sheng-Yuan Hsueh, Tainan, TW;

Chi-Horn Pai, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/80 (2025.01);
U.S. Cl.
CPC ...
H10D 84/811 (2025.01); H10D 84/0142 (2025.01); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

The present disclosure provides, the semiconductor device includes a substrate, a first transistor, a capacitor, and two first plugs. The substrate has a high-voltage region and a capacitor region. The first transistor is disposed in the high-voltage region, and includes a first gate dielectric layer, a first gate electrode, and a first capping layer. The capacitor is disposed in the capacitor region and includes a second gate electrode, a second capping layer, a dielectric layer, and a conductive layer. The two first plugs are disposed on the capacitor, wherein one of the two first plugs penetrates through the second capping layer to directly contact the second gate electrode, and another one of the two first plugs directly contacts the conductive layer.


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