The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Jan. 23, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chun-Chieh Lu, Taipei, TW;

Carlos H. Diaz, Mountain View, CA (US);

Chih-Sheng Chang, Hsinchu, TW;

Cheng-Yi Peng, Taipei, TW;

Ling-Yen Yeh, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/324 (2006.01); H10D 1/68 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10D 64/689 (2025.01); H01L 21/02181 (2013.01); H01L 21/02189 (2013.01); H01L 21/02194 (2013.01); H01L 21/0228 (2013.01); H01L 21/02304 (2013.01); H01L 21/02356 (2013.01); H01L 21/324 (2013.01); H10D 1/68 (2025.01); H10D 30/0415 (2025.01); H10D 30/62 (2025.01); H10D 30/701 (2025.01); H10D 64/017 (2025.01); H10D 64/033 (2025.01); H10D 64/691 (2025.01);
Abstract

In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.


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