The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2025
Filed:
Dec. 23, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Kimberly Pierce, Beaverton, OR (US);
Marni Nabors, Hillsboro, OR (US);
Mark Phillips, Hillsboro, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10D 84/00 (2025.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
H01L 23/585 (2013.01); H01L 21/768 (2013.01); H01L 23/528 (2013.01); H10D 84/00 (2025.01); G03F 7/2004 (2013.01);
Abstract
Devices, systems, and methods are described related to providing nonlinear lithographic seams, such as rectilinear lithographic seams, between adjacent fields of an integrated circuit die. Such nonlinear lithographic seams include lithographic enabling structures formed in co-planar layers with respect to functional structures in functional units of the fields of the integrated circuit die. Providing nonlinear lithographic seams improves layout efficiency of the functional units of the integrated circuit die.