The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Mar. 29, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Carlton Hanna, San Jose, CA (US);

Georg Seidemann, Landshut, DE;

Eduardo De Mesa, Munich, DE;

Abdallah Bacha, Munich, DE;

Lizabeth Keser, San Diego, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/14 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/145 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 25/0655 (2013.01); H01L 23/5381 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2924/3511 (2013.01);
Abstract

An electronic device comprises a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material; a stiffening layer including one of a ceramic or glass, the stiffening layer including a first surface contacting a first surface of the first RDL and including a through layer via (TLV); and multiple integrated circuit (ICs) arranged on a second surface of the first RDL and including bonding pads, wherein the conductive traces of the first RDL provide electrical continuity between at least one bonding pad of the ICs and at least one TLV of the stiffening layer.


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