The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Apr. 25, 2024
Applicant:

Ii-vi Advanced Materials, Llc, Pine Brook, NJ (US);

Inventors:

Adolf Schoner, Hässelby, SE;

Sergey Reshanov, Upplands Väsby, SE;

Assignee:

II-VI ADVANCED MATERIALS, LLC, Pine Brook, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/02 (2006.01); H01L 21/304 (2006.01); H10D 62/832 (2025.01);
U.S. Cl.
CPC ...
H01L 21/7813 (2013.01); H01L 21/02032 (2013.01); H01L 21/304 (2013.01); H10D 62/8325 (2025.01);
Abstract

There is provided a method for manufacturing a SiC device wafer comprising the steps: a) slicing and polishing a SiC boule to thicker substrates compared to the usual thickness in the prior art, b) creating a device wafer on the substrate, c) removing the device wafer from the remaining substrate, d) adding SiC to the remaining substrate so that the original thickness of the substrate is essentially restored, and repeating steps b)-d). The removal of the device wafer can be made for instance by laser slicing. Advantages include that the SiC material loss is significantly decreased and the boule material used for device wafers is considerably increased, the substrates become more stable especially during high temperature processes, the warp and bow is reduced, the risk of breakage is decreased.


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