The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Nov. 08, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Scott E. Smith, Boise, ID (US);

Sujeet Ayyapureddi, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/42 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); H03M 13/05 (2006.01); H03M 13/29 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G06F 11/1016 (2013.01); G06F 11/102 (2013.01); G06F 11/1044 (2013.01); G11C 29/52 (2013.01); H03M 13/05 (2013.01); H03M 13/2906 (2013.01); G06F 2211/104 (2013.01);
Abstract

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.


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