Memory device and method for operating memory device

Abstract

A memory device is provided. The memory device includes a compute-in-memory (CIM) array, capacitor circuit pairs, a first switch circuit and an analog-to-digital converter. The CIM array includes bit cells arranged in columns, in which the CIM array generates, in response to an input vector and a stored vector in the bit cells, accumulation results. The capacitor circuit pairs receive the accumulation results through bit lines, in which portions, in one of the columns, of the bit cells and a corresponding one of capacitor circuit pairs are coupled to a corresponding bit line of the bit lines. The first switch circuit is coupled to the capacitor circuit pairs is switched to generate, based on the accumulation results, weight mean results in one capacitor circuit in each of the plurality of capacitor circuit pairs. The analog-to-digital converter generates, according to the plurality of weight mean results, a multiply-and-accumulate result.