The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

May. 26, 2023
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Brittany Hedrick, Lagrangeville, NY (US);

Ian Melville, Highland, NY (US);

Michael David Webster, Poughkeepsie, NY (US);

Harry Cox, Rifton, NY (US);

Jorge Lubguban, Danbury, CT (US);

Sarah Knickerbocker, East Fishkill, NY (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/12 (2006.01); F21V 8/00 (2006.01); G02B 6/122 (2006.01);
U.S. Cl.
CPC ...
G02B 6/0065 (2013.01); G02B 6/1225 (2013.01); G02B 6/1228 (2013.01); G02B 6/12011 (2013.01);
Abstract

Structures for a photonics chip that include a cavity or groove and methods of forming same. The structure comprises a semiconductor substrate including a first opening, a back-end-of-line stack on the semiconductor substrate, and a dielectric layer on the back-end-of-line stack. The back-end-of-line stack includes a pad, and the dielectric layer includes a second opening that extends to the pad. The structure further comprises an electrical interconnect inside the second opening in the dielectric layer. The electrical interconnect includes a sidewall that is separated in a lateral direction from the dielectric layer by a gap.


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