The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Nov. 17, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Hung Yeh, Hsinchu, TW;

Wun-Jie Lin, Hsinchu, TW;

Jam-Wem Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 89/60 (2025.01); H02H 9/04 (2006.01);
U.S. Cl.
CPC ...
H10D 89/811 (2025.01); H02H 9/046 (2013.01); H10D 89/911 (2025.01);
Abstract

An apparatus for providing electrostatic discharge (ESD) immunity and a method for fabricating the same are disclosed herein. The apparatus comprises a field effect transistor (FET) formed on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process, a metal interconnect layer formed on top of the FEOL layer during a back-end-of-line (BEOL) process, wherein the metal interconnect layer comprises a plurality interconnects configured to interconnect the FET to a plurality of components formed on the semiconductor substrate, a power delivery network (PDN) formed under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process, and a through substrate resistive component formed between the FEOL and B-BEOL layers, wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and second contact is connected, through the PDN, to a power supply rail.


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