The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2025
Filed:
Dec. 10, 2021
Intel Corporation, Santa Clara, CA (US);
Carleton L. Molnar, Northborough, MA (US);
Adel A. Elsherbini, Tempe, AZ (US);
Tanay Karnik, Portland, OR (US);
Shawna M. Liff, Scottsdale, AZ (US);
Robert J. Munoz, Round Rock, TX (US);
Julien Sebot, Portland, OR (US);
Johanna M. Swan, Scottsdale, AZ (US);
Nevine Nassif, Arlington, MA (US);
Gerald S. Pasdast, San Jose, CA (US);
Krishna Bharath, Phoenix, AZ (US);
Neelam Chandwani, Portland, OR (US);
Dmitri E. Nikonov, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.