The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Aug. 16, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuo-Ming Wu, Zhubei, TW;

Hau-Yi Hsiao, Chiayi, TW;

Ping-Tzu Chen, Tainan, TW;

Chung-Jen Huang, Tainan, TW;

Sheng-Chau Chen, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/80 (2013.01); H01L 23/562 (2013.01); H01L 24/08 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80007 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/3512 (2013.01); H01L 2924/35121 (2013.01);
Abstract

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes bonding a first semiconductor wafer to a second semiconductor wafer. A bond interface is disposed between the first and second semiconductor wafers. The first semiconductor wafer has a peripheral region laterally surrounding a central region. A support structure is formed between a first outer edge of the first semiconductor wafer and a second outer edge of the second semiconductor wafer. The support structure is disposed within the peripheral region. A thinning process is performed on the second semiconductor wafer.


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