The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Apr. 18, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Myeongho Hong, Suwon-si, KR;

Dowon Kim, Anyang-si, KR;

Jangbae Son, Incheon, KR;

Seokwoo Yoon, Cheonan-si, KR;

Kyomuk Lim, Sejong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H05K 1/18 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/02 (2013.01); H01L 24/08 (2013.01); H01L 24/19 (2013.01); H01L 24/95 (2013.01); H05K 1/185 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 22/34 (2013.01); H01L 23/5381 (2013.01); H01L 25/0655 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02333 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/08235 (2013.01); H01L 2224/12105 (2013.01); H01L 2924/1815 (2013.01);
Abstract

A package structure includes a core substrate including a substrate base including a plurality of first cavities and a plurality of second cavities, a plurality of blocks in the plurality of second cavities; and a plurality of bridge structures that extend between each of the plurality of blocks and the substrate base, a plurality of semiconductor chips in the plurality of first cavities, and a molding layer configured to cover the core substrate and the plurality of semiconductor chips, a portion of the molding layer being in the plurality of first cavities and the plurality of second cavities.


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