The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Dec. 21, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek A. Sharma, Portland, OR (US);

Wilfred Gomes, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H10B 12/00 (2023.01); H10D 62/832 (2025.01); H10D 62/85 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H10B 12/09 (2023.02); H10B 12/315 (2023.02); H10B 12/50 (2023.02); H10D 62/8325 (2025.01); H10D 62/8503 (2025.01); H10D 64/01 (2025.01); H10D 64/514 (2025.01); H10D 64/683 (2025.01); H10D 64/691 (2025.01);
Abstract

Memory device architectures including integrated high voltage planar transistor support circuitry underlying memory cell arrays are discussed related to improving density and device performance Such memory device architectures include planar transistors having wide band gap channel materials integrated with memory cell arrays using a number of metallization layers. The metallization layers between the planar transistors and the memory cells are predominantly tungsten and the metallization layers in which the memory cells are embedded are predominantly a metal other than tungsten.


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