The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2025
Filed:
Mar. 13, 2024
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Sheyang Ning, San Jose, CA (US);
Lawrence Celso Miranda, San Jose, CA (US);
Tomoko Ogura Iwasaki, San Jose, CA (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/16 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01); G11C 16/3481 (2013.01);
Abstract
A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, and wordlines coupled with first and second pillars. Control logic may cause wordlines to be discharged after a program pulse is applied to selected wordline. The control logic may apply a supply voltage to second data line to cause a voltage of second pillar to float. The control logic may apply a ground voltage to the first data line to inhibit soft erase associated with the selected wordline via first pillar.