The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Apr. 08, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Guan-Lin Chen, Hsinchu, TW;

Kuo-Cheng Chiang, Hsinchu, TW;

Shi Ning Ju, Hsinchu, TW;

Jung-Chien Cheng, New Taipei, TW;

Chih-Hao Wang, New Taipei, TW;

Kuan-Lun Cheng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10B 10/00 (2023.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/85 (2025.01); H10B 10/125 (2023.02); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01);
Abstract

A structure includes a first dielectric feature extending along a first direction, the first dielectric feature having a first side and a second side opposing the first side. The structure includes a first semiconductor layer disposed adjacent the first side of the first dielectric feature, the first semiconductor layer extending along a second direction perpendicular to the first direction. The structure includes a CESL in contact with the first dielectric feature and a portion of the first semiconductor layer, an ILD layer in contact with the CESL and a portion of the first semiconductor layer. The structure further includes a second dielectric feature extending along the first direction, the second dielectric feature including a first dielectric layer in contact with the CESL and a portion of the first semiconductor layer, and a second dielectric layer in contact with the first dielectric layer and a portion of the first semiconductor layer.


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