The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Dec. 29, 2021
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventor:

Darrell Glenn Hill, Chandler, AZ (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/00 (2025.01); H01L 21/76 (2006.01); H01L 21/765 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/85 (2025.01);
U.S. Cl.
CPC ...
H10D 64/111 (2025.01); H01L 21/7605 (2013.01); H01L 21/765 (2013.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/8503 (2025.01);
Abstract

A transistor device includes a semiconductor substrate and a gate structure at the upper surface of the substrate. The gate structure is non-planar and includes a metal gate electrode with first and second sidewalls. A first dielectric layer is present over the gate structure. The first dielectric layer includes a first portion that overlies the first sidewall and a second portion that overlies the second sidewall. A portion of a conductive layer over the first dielectric layer forms a field plate with a first portion proximate to the second sidewall of the gate structure. A dielectric sidewall spacer on the first portion of the field plate is formed from a portion of a second dielectric layer, and the dielectric sidewall spacer does not contact the first dielectric layer.


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