The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Jan. 03, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Ta-Chun Lin, Hsinchu, TW;

Kuo-Hua Pan, Hsinchu, TW;

Jhon Jhy Liaw, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/62 (2025.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H10D 30/024 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01);
Abstract

A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material. The method further includes patterning the semiconductor stack within the first region to form a nanostructure stack, patterning the second type of semiconductor material within the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure.


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