The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Jun. 16, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Wei Jiang, Hsinchu, TW;

Sheng-Chih Lai, Hsinchu County, TW;

Feng-Cheng Yang, Hsinchu County, TW;

Chung-Te Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 23/528 (2006.01); H01L 51/30 (2006.01); H10B 51/30 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01);
U.S. Cl.
CPC ...
H10D 30/0415 (2025.01); H01L 23/5283 (2013.01); H10B 51/30 (2023.02); H10D 30/701 (2025.01);
Abstract

A transistor includes a gate electrode, a ferroelectric layer, a channel layer, a gas impermeable layer, a dielectric layer, a source line and a bit line. The ferroelectric layer is disposed on the gate electrode. The channel layer is disposed on the ferroelectric layer. The gas impermeable layer is disposed in between the channel layer and the gate electrode, and in contact with the ferroelectric layer. The dielectric layer is surrounding the ferroelectric layer and the channel layer, and in contact with the gas impermeable layer. The source line and the bit line are embedded in the dielectric layer and connected to the channel layer.


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