logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12464725 B1

PDFFull Text
Date of Patent:
Nov. 04, 2025

Filed:

Mar. 28, 2022

3d circuit structure with stairstep contact configuration

Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Meng-Yen Wu, Taichung, TW;

Teng-Hao Yeh, Hsinchu, TW;

Assignee:

MACRONIX INTERNATIONAL CO., LTD., Hsinchu, TW;

Attorneys:

Andrew L. Dunlap

Haynes Beffel & Wolfeld LLP

Primary Examiner:

Moin M Rahman

Int. Cl.
CPC ...
H10B 43/40 (2023.01); G11C 16/04 (2006.01); H01L 23/522 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 43/40 (2023.02); G11C 16/0483 (2013.01); H01L 23/5226 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

Circuit structures to improve manufacturing yield in complex 3D circuits have a first stack of conductors and a second stack of conductors having memory regions and contact regions. Conductors of the first stack have stepped arrangement in the contact region to provide landing areas on the conductors. Connecting circuits connect the landing areas of conductive layers in the first stack to through-stack conductors in vias in the second stack, to connect to circuitry below the stack. The memory regions include arrays of vertical memory pillars. The connecting circuits include interlayer connectors contacting landing areas in the first stack, extending to patterned conductors over the first and second stacks. The patterned conductors can include links from interlayer connectors of the first stack to through-stack connectors of the second stack. The circuit structure can include a plurality of structural vertical pillars in the contact region of the first stack.

Find Patent Forward Citations

Wu, Meng-Yen. (2025). 3d circuit structure with stairstep contact configuration (U.S. Patent No. 12464725). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12464725

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…