The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Feb. 04, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Lifang Xu, Boise, ID (US);

Richard J. Hill, Boise, ID (US);

Yoshiaki Fukuzumi, Kanagawa, JP;

Paolo Tessariol, Arcore, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11556 (2017.01); H01L 21/3205 (2006.01); H01L 21/4763 (2006.01); H01L 21/70 (2006.01); H10B 12/00 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); H01L 21/3205 (2013.01); H01L 21/4763 (2013.01); H01L 21/70 (2013.01); H10B 12/0387 (2023.02); H10B 41/10 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); G11C 16/0483 (2013.01);
Abstract

Memory circuitry comprising strings of memory cells comprising memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the memory blocks extend from the memory-array region into a stair-step region. Individual of the memory blocks in the stair-step region comprise a flight of operative stairs. Individual of the operative stairs comprise one of the conductive tiers. At least some immediately-laterally-adjacent of the individual memory blocks in the stair-step region have their flights of operative stairs laterally-separated by a stack comprising two vertically-alternating different-composition insulative materials. Other embodiments, including method, are disclosed.


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