The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Oct. 01, 2021
Applicant:

Kepler Computing Inc., San Francisco, CA (US);

Inventors:

Noriyuki Sato, Hillsboro, OR (US);

Debraj Guhabiswas, Berkeley, CA (US);

Tanay Gosavi, Portland, OR (US);

Niloy Mukherjee, San Ramon, CA (US);

Amrita Mathuriya, Portland, OR (US);

Sasikanth Manipatruni, Portland, OR (US);

Assignee:

Kepler Computing Inc., San Francisco, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); G11C 11/22 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H10B 53/20 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 23/5384 (2013.01); H01L 24/82 (2013.01); H01L 25/0652 (2013.01); H10B 53/20 (2023.02); G11C 11/221 (2013.01); H01L 2225/06544 (2013.01);
Abstract

An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.


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