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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12462328 B1

PDFFull Text
Date of Patent:
Nov. 04, 2025

Filed:

Jul. 13, 2023

Coordination and increased utilization of graphics processors during inference

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek R. Appu, El Dorado Hills, CA (US);

Altug Koker, El Dorado Hills, CA (US);

John C. Weast, Portland, OR (US);

Mike B. Macpherson, Portland, OR (US);

Linda L. Hurd, Cool, CA (US);

Sara S. Baghsorkhi, San Jose, CA (US);

Justin E. Gottschlich, Santa Clara, CA (US);

Prasoonkumar Surti, Folsom, CA (US);

Chandrasekaran Sakthivel, Sunnyvale, CA (US);

Liwei Ma, Beijing, CN;

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Kamal Sinha, Cordova, CA (US);

Joydeep Ray, Folsom, CA (US);

Balaji Vembu, Folsom, CA (US);

Sanjeev Jahagirdar, Folsom, CA (US);

Vasanth Ranganathan, EL Dorado Hills, CA (US);

Dukhwan Kim, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Jaffery Watson Hamilton & DeSanctis LLP

Primary Examiner:

Jacinta M Crawford

Int. Cl.
CPC ...
G06T 1/20 (2006.01); G06F 9/46 (2006.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01); G06N 3/084 (2023.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06F 9/46 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G06N 3/044 (2023.01); G06N 3/084 (2013.01);
Abstract

A mechanism is described for detecting, at training time, information related to one or more tasks to be performed by the one or more processors according to a training dataset for a neural network, analyzing the information to determine one or more portions of hardware of a processor of the one or more processors that is configurable to support the one or more tasks, configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks, and monitoring utilization of the hardware via a hardware unit of the graphics processor and, via a scheduler of the graphics processor, adjusting allocation of the one or more tasks to the one or more portions of the hardware based on the utilization.

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