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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12462084 B1

PDFFull Text
Date of Patent:
Nov. 04, 2025

Filed:

Jul. 28, 2022

Power envelope analysis for the thermal optimization of multi-chip modules

Applicant:

Stats Chippac Pte. Ltd., Singapore, SG;

Inventors:

Chien Ouyang, Pleasanton, CA (US);

Xiao Gu, JiangSu, CN;

Yonghyuk Jeong, Incheon, KR;

Michael Mingliang Liu, Fullerton, CA (US);

Assignee:

STATS ChipPAC Pte. Ltd., Singapore, SG;

Attorneys:

Brian M. Kaufman

Robert D. Atkins

PATENT LAW GROUP: Atkins and Associates, P.C.

Primary Examiner:

Jack Chiang

Assistant Examiner:

Brandon undefined Bowers

Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 17/16 (2006.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); H01L 23/427 (2006.01); H01L 25/16 (2023.01); G06F 113/18 (2020.01); G06F 115/06 (2020.01); G06F 115/12 (2020.01); G06F 119/02 (2020.01); G06F 119/06 (2020.01); G06F 119/08 (2020.01); G06F 119/22 (2020.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G06F 30/373 (2020.01); G06F 17/16 (2013.01); G06F 30/367 (2020.01); H01L 23/427 (2013.01); H01L 25/162 (2013.01); H01L 25/165 (2013.01); G06F 2113/18 (2020.01); G06F 2115/06 (2020.01); G06F 2115/12 (2020.01); G06F 2119/02 (2020.01); G06F 2119/06 (2020.01); G06F 2119/08 (2020.01); G06F 2119/22 (2020.01); H01L 24/16 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1616 (2013.01); H01L 2924/16196 (2013.01); H01L 2924/16235 (2013.01); H01L 2924/16251 (2013.01); H01L 2924/1627 (2013.01); H01L 2924/351 (2013.01); H01L 2924/37001 (2013.01);
Abstract

A semiconductor device is made by calculating a thermal resistance matrix for the semiconductor device. A plurality of maximum junction temperatures for the plurality of die of the semiconductor device is selected. A plurality of power envelope surfaces are calculated for the semiconductor device based on the thermal resistance matrix and the maximum junction temperatures. A plurality of powers is selected for the plurality of die. The plurality of powers are compared against the plurality of power envelope surfaces to determine a plurality of risk values.

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