The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Apr. 24, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Bo-Feng Young, Taipei, TW;

Sheng-Chen Wang, Hsinchu, TW;

Sai-Hooi Yeong, Zhubei, TW;

Yu-Ming Lin, Hsinchu, TW;

Mauricio Manfrini, Zhubei, TW;

Han-Jong Chia, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2023.01); H10B 61/00 (2023.01); H10D 30/67 (2025.01); H10D 62/80 (2025.01); H10D 99/00 (2025.01);
U.S. Cl.
CPC ...
H10B 63/30 (2023.02); H10B 61/22 (2023.02); H10D 30/6755 (2025.01); H10D 62/80 (2025.01); H10D 99/00 (2025.01);
Abstract

The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device has a substrate and a lower interconnect metal line disposed over the substrate. The memory device also has a selector channel disposed over the lower interconnect metal line and a selector gate electrode wrapping around a sidewall of the selector channel and separating from the selector channel by a selector gate dielectric. The memory device also has a memory cell disposed over and electrically connected to the selector channel and an upper interconnect metal line disposed over the memory cell. By placing the selector within the back-end interconnect structure, front-end space is saved, and more integration flexibility is provided.


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