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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12456661 B1

PDFFull Text
Date of Patent:
Oct. 28, 2025

Filed:

Jun. 11, 2021

Semiconductor structure having a silicon active layer formed over a sige etch stop layer and an insulating layer with a through silicon via (tsv) passed therethrough

Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Yu-Hung Cheng, Tainan, TW;

Shih-Pei Chou, Tainan, TW;

Yeur-Luen Tu, Taichung, TW;

Alexander Kalnitsky, San Francisco, CA (US);

Tung-I Lin, Tainan, TW;

Wei-Li Chen, Tainan, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;

Attorneys:

WPAT LAW

Anthony King

Primary Examiner:

Anh D Mai

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/20 (2006.01); H01L 21/306 (2006.01); H01L 21/683 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H10D 86/01 (2025.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/2007 (2013.01); H01L 21/30604 (2013.01); H01L 21/6835 (2013.01); H01L 21/76256 (2013.01); H01L 21/76829 (2013.01); H01L 21/76898 (2013.01); H10D 86/0214 (2025.01); H01L 2221/68359 (2013.01);
Abstract

The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.

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