The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Nov. 23, 2022
Applicants:

Stmicroelectronics (Grand Ouest) Sas, Le Mans, FR;

Stmicroelectronics (Alps) Sas, Grenoble, FR;

Inventors:

Loic Pallardy, Rouillon, FR;

Nicolas Anquet, Grenoble, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0622 (2013.01); G06F 3/0637 (2013.01); G06F 3/0673 (2013.01); G06F 12/1441 (2013.01); G06F 12/1458 (2013.01);
Abstract

In accordance with an embodiment, a system on chip includes: a plurality of master equipment; a plurality of slave resources, where a slave resource of the plurality of slave resources comprises a memory device includes a first memory area; an interconnection circuit; and a check circuit. A first master equipment is configured to define initial access rights for the first memory area, and to delegate access management of the first memory area to a second master equipment. The second master equipment is configured to define for the first memory area, particular access rights from the initial access rights associated with the first memory area and access right rules; and the check circuit is configured to check whether a transaction intended for the first memory area is indeed authorized to access the first memory area using applicable access rights associated with the first memory area.


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