The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Apr. 11, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Ming-Chi Wu, Kaohsiung, TW;

Chun-Chieh Fang, Hsinchu, TW;

Bo-Chang Su, Tainan, TW;

Chien Nan Tu, Kaohsiung, TW;

Yu-Lung Yeh, Kaohsiung, TW;

Kun-Yu Lin, Tainan, TW;

Shih-Shiung Chen, Tainan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); H01L 21/3065 (2006.01); H01L 21/311 (2006.01); H01L 21/3205 (2006.01); H01L 21/762 (2006.01); H10F 39/12 (2025.01); H10F 39/18 (2025.01);
U.S. Cl.
CPC ...
H10F 39/807 (2025.01); H01L 21/76224 (2013.01); H10F 39/199 (2025.01); H10F 39/8067 (2025.01); H01L 21/3065 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/32051 (2013.01); H10F 39/18 (2025.01); H10F 39/8053 (2025.01); H10F 39/8063 (2025.01);
Abstract

A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.


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