The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

May. 04, 2023
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Germain Bossu, Dresden, DE;

Nigel Chan, Dresden, DE;

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 1/66 (2025.01); H10D 1/00 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01);
U.S. Cl.
CPC ...
H10D 86/201 (2025.01); H10D 1/047 (2025.01); H10D 1/66 (2025.01); H10D 86/01 (2025.01);
Abstract

An integrated circuit (IC) structure, including a semiconductor-on-insulator (SOI) substrate, the SOI substrate including a buried insulator layer over a base semiconductor layer, and a semiconductor-on-insulator (SOI) layer over the buried insulator layer. The IC structure further includes a gate over a gate dielectric layer over the SOI layer. The IC structure includes an n-type metal-oxide semiconductor (n-MOS) capacitor. The n-MOS capacitor includes an n-well under the buried insulator layer, and an n-type semiconductor adjacent a first side of the gate. The IC structure also includes a p-type metal-oxide semiconductor (p-MOS) capacitor adjacent the n-MOS capacitor and includes a p-well adjacent the n-well and a p-type semiconductor adjacent a second side of the gate. The gate is electrically connected only to the n-MOS capacitor and the p-MOS capacitor.


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