The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Jun. 04, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chien-Yuan Chen, Taichung, TW;

Kuo-Feng Yu, Hsinchu County, TW;

Jian-Hao Chen, Hsinchu, TW;

Chih-Yu Hsu, Hsinchu County, TW;

Yao-Teng Chuang, Hsinchu, TW;

Shan-Mei Liao, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/0415 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 30/701 (2025.01); H10D 62/121 (2025.01); H10D 84/0144 (2025.01); H10D 84/83 (2025.01); H01L 21/76864 (2013.01);
Abstract

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece comprising a first channel member directly over a first region of a substrate and a second channel member directly over the first channel member, the first channel member being vertically spaced apart from the second channel member, conformally forming a dielectric layer over the workpiece, conformally depositing a dipole material layer over the dielectric layer, after the depositing of the dipole material layer, performing a thermal treatment process to the workpiece, after the performing of the thermal treatment process, selectively removing the dipole material layer, and forming a gate electrode layer over the dielectric layer.


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