The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Feb. 23, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Guan-Lin Chen, Hsinchu, TW;

Kuo-Cheng Chiang, Hsinchu County, TW;

Chih-Hao Wang, Hsinchu County, TW;

Shi Ning Ju, Hsinchu, TW;

Jui-Chien Huang, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/3105 (2006.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/17 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H01L 21/02532 (2013.01); H01L 21/30604 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6735 (2025.01); H10D 62/292 (2025.01); H10D 64/015 (2025.01); H10D 64/021 (2025.01); H01L 21/02271 (2013.01); H01L 21/26513 (2013.01); H01L 21/31053 (2013.01); H01L 21/76224 (2013.01); H10D 64/017 (2025.01);
Abstract

The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.


Find Patent Forward Citations

Loading…