The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2025
Filed:
Aug. 26, 2021
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Chao-I Wu, Zhubei, TW;
Yu-Ming Lin, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Abstract
A disclosed memory structure includes a first memory region including a first memory array of SRAM memory devices, a second memory region including a second memory array of 1T1C memory devices, and a third memory region including a third memory array of FeFET memory devices. The memory structure further includes at least one data bus laterally extending across the first memory region, the second memory region, and third memory region and configured to provide data transfer among the first memory array, the second memory array, and the third memory array. The memory structure further includes a plurality of peripheral circuit devices formed at a semiconductor material layer of the memory structure, the peripheral circuit devices configured to control the first memory array, the second memory array, and the third memory array. At least one of the second memory array and the third memory array may be a 3-dimensional memory array.