The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2025
Filed:
Sep. 03, 2021
Kepler Computing Inc., San Francisco, CA (US);
Amrita Mathuriya, Portland, OR (US);
Ikenna Odinaka, Durham, NC (US);
Rajeev Kumar Dokania, Beaverton, OR (US);
Rafael Rios, Austin, TX (US);
Sasikanth Manipatruni, Portland, OR (US);
Kepler Computing Inc., San Francisco, CA (US);
Abstract
A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.