The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Apr. 11, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Blaine J. Thurgood, Nampa, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); G11C 5/04 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); G11C 5/04 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/1434 (2013.01);
Abstract

A semiconductor device assembly is provided. The assembly comprises a package substrate, a first stack of semiconductor dies having a first set of planform dimensions disposed over a first location on the substrate, a second stack of semiconductor dies having a second set of planform dimensions different from the first set disposed over a second location on the substrate, and an encapsulant at least partially encapsulating the substrate, the first stack and the second stack. The first stack of semiconductor dies has a first planform area, the second stack of semiconductor dies has a second planform area, and a sum of the first and second planform areas can be at least 50%, 67%, 75%, or even more of an area of the package substrate.


Find Patent Forward Citations

Thurgood, Blaine. (2025). Semiconductor device assemblies including multiple stacks of different semiconductor dies (U.S. Patent No. 12451463). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12451463

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…