The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Jul. 10, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Hochul Lee, Los Angeles, CA (US);

Anil Chowdary Kota, San Diego, CA (US);

Dhvani Sheth, San Diego, CA (US);

Bin Liang, San Diego, CA (US);

Chulmin Jung, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/08 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1069 (2013.01); G11C 7/08 (2013.01); G11C 7/1012 (2013.01); G11C 7/1096 (2013.01);
Abstract

A memory is provided with a pair of banks including a first bank of bitcells and a second bank of bitcells. An I/O circuit for the pair of banks includes a shared write path configured to couple a write driver input signal to the first bank of bitcells responsive to an assertion of a write enable signal for the first bank of bitcells and to couple the write driver input signal to the second bank of bitcells responsive to an assertion of a write enable signal for the second bank of bitcells. The I/O circuit also includes a shared read path configured to couple a data bit output signal from the first bank of bitcells to a sense amplifier responsive to a de-assertion of the write enable signal for the first bank of bitcells and to couple a data bit output signal from the second bank of bitcells to the sense amplifier responsive to a de-assertion of the write enable signal for the second bank of bitcells. The shared read and write paths are further configured to operate simultaneously so that a write operation to one of the banks may occur while a read operation occurs to another one of the banks.


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