The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Nov. 22, 2024
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Shyue Seng Tan, Singapore, SG;

Kian Ming Ng, Singapore, SG;

Eng Huat Toh, Singapore, SG;

Assignee:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/30 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10D 30/701 (2025.01); H10B 51/30 (2023.02); H10D 30/0415 (2025.01); H10D 64/033 (2025.01); H10D 64/689 (2025.01);
Abstract

A ferroelectric transistor (FeFET) memory device includes a metal gate, a gate dielectric layer adjacent to the metal gate, a semiconductor channel layer adjacent to the gate dielectric layer, a metal drain electrode, and a metal source electrode recessed into the semiconductor channel layer. The metal gate may be oriented above or below the metal source and drain electrodes with respect to a semiconductor substrate.


Find Patent Forward Citations

Tan, Shyue. (2025). Fe-fet structure with buried electrode (U.S. Patent No. 12446266). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12446266

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…