The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2025
Filed:
Aug. 05, 2022
Applicant:
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Inventors:
Assignee:
YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/68 (2025.01); G11C 16/04 (2006.01); H01L 21/762 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6894 (2025.01); G11C 16/0483 (2013.01); H01L 21/76224 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10D 30/0411 (2025.01); H10D 30/0413 (2025.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10D 30/699 (2025.01); H10D 64/035 (2025.01); H10D 64/037 (2025.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02);
Abstract
A semiconductor device and a method for manufacturing the same, and a NAND memory device are disclosed. The method comprises: forming a substrate that comprises a first active region and an isolation region; forming a first groove between the isolation region and the first channel region, the first groove being partially located in the isolation region, and not penetrating through the isolation region; forming a first gate insulating layer covering the first groove and the first channel region; forming a first gate on the first gate insulating layer, the first gate covering the first channel region and filling the first groove.