The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Feb. 23, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chun-Hsiung Tsai, Xinpu Township, TW;

Shahaji B. More, Hsinchu, TW;

Yu-Ming Lin, Hsinchu, TW;

Clement Hsingjen Wann, Carmel, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H10B 12/00 (2023.01); H10D 1/66 (2025.01); H10D 1/68 (2025.01); H10F 39/00 (2025.01);
U.S. Cl.
CPC ...
H10D 1/692 (2025.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 24/18 (2013.01); H01L 24/25 (2013.01); H10B 12/038 (2023.02); H10B 12/37 (2023.02); H10D 1/665 (2025.01); H10F 39/811 (2025.01); H01L 2224/821 (2013.01);
Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.


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