The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2025
Filed:
May. 31, 2023
Kepler Computing Inc., San Francisco, CA (US);
Mauricio Manfrini, Heverlee, BE;
Noriyuki Sato, Hillsboro, OR (US);
James David Clarkson, El Sobrante, CA (US);
Abel Fernandez, Berkeley, CA (US);
Somilkumar J. Rathi, San Jose, CA (US);
Niloy Mukherjee, San Ramon, CA (US);
Tanay Gosavi, Portland, OR (US);
Amrita Mathuriya, Portland, OR (US);
Rajeev Kumar Dokania, Beaverton, OR (US);
Sasikanth Manipatruni, Portland, OR (US);
Kepler Computing Inc., San Francisco, CA (US);
Abstract
A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.