The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

May. 18, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Meng-Han Lin, Hsinchu, TW;

Han-Jong Chia, Hsinchu, TW;

Sai-Hooi Yeong, Zhubei, TW;

Chi On Chui, Hsinchu, TW;

Yu-Ming Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H10D 1/00 (2025.01); H10D 1/68 (2025.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10B 12/33 (2023.02); H10B 12/036 (2023.02); H10B 12/05 (2023.02); H10D 1/042 (2025.01); H10D 1/714 (2025.01); H10D 30/6735 (2025.01);
Abstract

An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.


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