The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2025
Filed:
Nov. 01, 2023
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Chih-Hsuan Lin, Hsinchu, TW;
Shao-Chang Huang, Hsinchu, TW;
Yeh-Ning Jou, Hsinchu, TW;
Chieh-Yao Chuang, Kaohsiung, TW;
Hwa-Chyi Chiou, Hsinchu, TW;
Wen-Hsin Lin, Hsinchu County, TW;
Kai-Chieh Hsu, Taoyuan, TW;
Ting-Yu Chang, Hsinchu County, TW;
Hsien-Feng Liao, Taichung, TW;
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION, Hsinchu, TW;
Abstract
An ESD protection circuit is coupled to a first pad and includes an ESD detection circuit, a P-type transistor, an N-type transistor, and a discharge circuit. The ESD detection circuit determines whether an ESD event occurs on the first pad to generate a detection signal at a first node. The P-type transistor comprises a source coupled to the first pad, a drain coupled to a second node, and a gate coupled to the first node. The N-type transistor comprises a drain coupled to the second node, a source coupled to a ground, and a gate coupled to a second pad. The discharge circuit is coupled between the first pad and the ground and controlled by a driving signal at the second node. When the ESD protection circuit is in an operation mode, the first pad receives a first voltage, and a second pad receives a second voltage.