The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Dec. 01, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tao Yi Hung, Hsinchu, TW;

Ming-Fang Lai, Hsinchu, TW;

Li-Wei Chu, Hsinchu, TW;

Wun-Jie Lin, Hsinchu, TW;

Jam-Wem Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01); H02H 1/00 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 89/60 (2025.01);
U.S. Cl.
CPC ...
H02H 9/046 (2013.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H10D 89/611 (2025.01); H10D 89/817 (2025.01); H10D 89/911 (2025.01); H10D 89/921 (2025.01); H02H 1/0007 (2013.01);
Abstract

A clamp circuit includes an electrostatic discharge (ESD) detection circuit coupled between a first node and a second node. The clamp circuit further includes a first transistor of a first type. The first transistor has a first gate coupled to at least the ESD detection circuit by a third node, a first drain coupled to the first node and a first source coupled to the second node. The clamp circuit further includes a charging circuit coupled between the second node and the third node, and configured to charge the third node during an ESD event at the second node.


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