The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2025
Filed:
Jan. 10, 2023
Applicant:
Changxin Memory Technologies, Inc., Anhui, CN;
Inventors:
Xiaofei Sun, Hefei, CN;
Changhao Quan, Hefei, CN;
Assignee:
CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/36 (2006.01); H01L 23/42 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/36 (2013.01); H01L 23/42 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 25/0652 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01);
Abstract
A semiconductor package structure is provided. The semiconductor package structure includes: a first package structure, including an intermediary layer and a molding compound, where a plurality of first connection pads are disposed on the intermediary layer, and the molding compound wraps the intermediary layer and is coplanar to the plurality of first connection pads; and a second package structure, disposed on the intermediary layer and electrically connected to the plurality of first connection pads. A gap is formed between the first package structure and the second package structure.