logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12444676 B1

PDFFull Text
Date of Patent:
Oct. 14, 2025

Filed:

Jun. 17, 2024

Self-aligned via for interconnect structure

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chieh-Han Wu, Kaohsiung, TW;

Cheng-Hsiung Tsai, Miaoli County, TW;

Chih Wei Lu, Hsinchu, TW;

Chung-Ju Lee, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

HAYNES AND BOONE, LLP

Primary Examiner:

Alonzo Chambliss

Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/76802 (2013.01); H01L 21/76816 (2013.01); H01L 21/76829 (2013.01); H01L 21/76843 (2013.01); H01L 21/7685 (2013.01); H01L 23/53209 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 24/32 (2013.01); H01L 24/37 (2013.01); H01L 2924/181 (2013.01);
Abstract

Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

Find Patent Forward Citations

Quick Actions:

Wu, Chieh-Han. (2025). Self-aligned via for interconnect structure (U.S. Patent No. 12444676). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12444676

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…