The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Feb. 07, 2023
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Keita Hirase, Kumamoto, JP;

Koji Tanaka, Kumamoto, JP;

Yukiyoshi Saito, Kumamoto, JP;

Keisuke Sasaki, Kumamoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/311 (2006.01); H01L 21/677 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67086 (2013.01); H01L 21/31111 (2013.01); H01L 21/67057 (2013.01); H01L 21/67161 (2013.01); H01L 21/67173 (2013.01); H01L 21/67742 (2013.01); H01L 21/67745 (2013.01); H01L 21/67748 (2013.01); H01L 21/67754 (2013.01); H01L 21/67757 (2013.01); H01L 21/67766 (2013.01);
Abstract

A substrate processing system includes: a carry-in/out section in which a cassette accommodating a plurality of substrates is carried in/out; a batch processing section in which a wafer lot including the plurality of substrates is collectively processed; a single-wafer processing section in which the substrates of the wafer lot is processed one by one; and an interface section that delivers the substrates between the batch processing section and the single-wafer processing section. The batch processing section includes: a processing bath in which the wafer lot is immersed and processed; and a first transfer device that transfers the wafer lot to the processing bath. The interface section includes: an immersion bath disposed outside a movement range of the first transfer device and that immerses the wafer lot; and a second transfer device that holds and transfers the wafer lot between the first transfer device and the immersion bath.


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